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A multicore chip usually provides a shared memory abstraction implemented by a cache coherence protocol. On-chip coherence can scale gracefully as the number of cores grows, and it plays a major role for general purpose applications. Besides, multicore architectures are likely to relax constraints on store atomicity and on the ordering between loads and stores. As a result, the validation of shared memory faces two main challenges: the higher number of valid execution behaviors and the larger coherence protocol's state space. This dissertation faces those challenges and targets an important design automation phase: the (pre-silicon) functional verification of the shared memory subsystem of a multicore chip, whose behavior is specified by a memory consistency model (MCM). The main scientific contribution is a novel approach to the building of MCM checkers, along with technical contributions on random test generation and directed test generation. The contributions were reported by two papers in a premier IEEE/ACM conference and two articles in the most prestigious IEEE journal on Computer Aided Design of Integrated Circuits and Systems.

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1	Marleson Graf(marleson.graf@posgrad.ufsc.br)
2	Luiz Villar dos Santos(luiz.santos@ufsc.br)

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#	Reference
1	Andrade, G. A. G., Graf, M., and dos Santos, L. C. V. (2020a). Chaining and Biasing: Test Generation Techniques for Shared-Memory Verification. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 39(3):728–741.
2	Andrade, G. A. G., Graf, M., Pfeifer, N., and dos Santos, L. C. V. (2018). Steep Coverage-ascent Directed Test Generation for Shared-memory Verification of Multicore Chips. In 2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).
3	Andrade, G. A. G., Graf, M., Pfeifer, N., and dos Santos, L. C. V. (2020b). A Directed Test Generator for Shared-Memory Verification of Multicore Chip Designs. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 39(12):5295–5303.
4	ARM (2018). ARM Architecture Reference Manual ARMv8, for ARMv8-A architecture profile.
5	Graf, M., Henschel, O. P., Alevato, R. P., and dos Santos, L. C. V. (2019). Spec&Check: An Approach to the Building of Shared-Memory Runtime Checkers for Multicore Chip Design Verification. In International Conference on Computer-Aided Design, pages 1–7.
6	Hennessy, J. L. and Patterson, D. A. (2017). Computer Architecture: A Quantitative Approach. Morgan Kaufmann Publishers Inc., San Francisco, CA, USA, 6th edition.
7	Martin, M. M., Hill, M. D., and Sorin, D. J. (2012). Why on-chip cache coherence is here to stay. Communications of the ACM, 55(7):78–89.
8	RISC-V (2019). The RISC-V Instruction Set Manual Volume I: Unprivileged ISA. Water-man, Andrew and Asanovi, Krste.

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