1 |
Bokhari, H. et al. (2015). SuperNet: Multimode interconnect architecture for manycore chips. In ACM/IEEE DAC.
|
|
2 |
Boyce, J. (2014), HM16: High Efficiency Video Coding Test Model (HM16) Encoder Description, JCTVC-R1002, Sapporo.
|
|
3 |
Cisco (2020) “Cisco Annual Internet Report (2018–2023) White Paper”, https://www.cisco.com/c/en/us/solutions/collateral/executive-perspectives/annual-internet-report/white-paper-c11-741490.html, June.
|
|
4 |
Grellert, M., Bampi, and Zatt, B. (2016). Complexity-scalable HEVC encoding. In IEEE PCS.
|
|
5 |
He, G. et al. (2015). High-throughput power-efficient VLSI architecture of fractional motion estimation for ultra-HD HEVC video encoding. In IEEE TVLSI, pages 3138-3142.
|
|
6 |
Indrusiak, L., Burns, A. and Nikolic, B. (2018). Buffer-aware bounds to multi-point progressive blocking in priority-preemptive NoCs. In IEEE DATE.
|
|
7 |
Lung, C. and Shen, C. (2019). Design and implementation of a highly efficient fractional motion estimation for the HEVC encoder. In JRTIP, pages 1541-1557.
|
|
8 |
Statista (2020) “Coronavirus impact on online traffic of selected industries worldwide in week ending April 26, 2020”, http://www.statista.com/statistics/1105486/coronavirus-traffic-impact-industry, June.
|
|
9 |
Sze, V., Budagavi, M. and Sullivan, G. (2014), High efficiency video coding (HEVC), Springer, USA, 1st edition.
|
|
10 |
Vanne, J. et al. (2012). Comparative Rate-Distortion-Complexity Analysis of HEVC and AVC Video Codecs. In IEEE TCSVT, pages 1885-1898.
|
|
11 |
Venkataramani, S. et al. (2015). Computing approximately, and efficiently. In IEEE DATE.
|
|